Power supply switching apparatus with severe overload detection

ABSTRACT

Power supply switching apparatus comprising an output switch for supplying power from a power supply to a load connected to an output terminal, a driver for controlling turn-on of said output switch, and a control signal generator for controlling said driver to produce a desired progressive turn-on characteristic. The apparatus also includes overload detection means responsive to a parameter of the load relative to a reference signal to provide a fault signal in case of detection of an overload condition after a turn-on phase of said output switch. The control signal generator is responsive to the reference signal to activate said overload detection means to provide a fault signal during the turn-on phase of the output switch even in presence of a severe overload condition at the output terminal.

FIELD OF THE INVENTION

This invention relates to power supply switching apparatus with overloaddetection and more particularly with capability for detecting severeoverload even during a turn-on phase.

BACKGROUND OF THE INVENTION

Power supply switching apparatus with overload detection, also referredto as a ‘smart power switch’, is used in many applications, includingautomotive equipment, especially to control vehicle lighting, forexample. It is particularly important to protect automotive wire harnessand printed circuit boards (PCB) during the turn-on of the power supply,as well as switch components of the power supply itself, even in theevent of severe short-circuits. The overload detector responds to anoverload by providing a fault signal that can be used to limit or avoiddamage. The present invention is particularly, but not exclusively,usable in such applications. Power switches with overload detection aredisclosed in Patent Applications PCT/EP2004/014895, PCT/EP2005/005208,PCT/EP2005/005211 and PCT/EP2005/005212.

Such smart power switches are subject to stringent power consumptionlimits during their quiescent operational mode and it is desirable toavoid powering and activating overload detection before the load is tobe turned on. Conveniently, the overload detector or sensor is poweredand activated by the same control signal as turns on the load. Certainconventional overload protection circuits use a sensor comprising asense resistor or Field Effect Transistor (‘FET’) and have a significantsettling time of a few hundred microseconds (μsecs) when they are turnedon; this already poses some issues for timely protection andprolongation of the reaction time should be minimised.

Moreover, power supply apparatus of this kind may be arranged to providea progressive build-up of output current during turn-on, known asround-shaping, which is implemented to meet Electro-MagneticCompatibility (‘EMC’) requirements, notably to reduce radio frequencyemissions. In order to achieve EMC requirements, the output slew-rate,that is to say the progressive turn-on of the output switch of the powersupply, is conveniently made dependent on the output voltage (Vout),which enables the use of a passive filter component to be avoided, forexample. The round-shaping can be achieved by sensing the output voltageto obtain a progressive variation of the control signal applied to theoutput switch, turning the output switch on progressively. However, thisprogressive turn-on also tends to prolong the overload detectionreaction time.

The overload detector responds to the load impedance by providing afault signal that can be used to limit or avoid damage. Overloaddetectors exist that function well to detect typical resistiveoverloads, that is to say where the load impedance still presents asignificant resistance even if it is an order of magnitude less than thenormal load, for example, at least after an acceptable initial timedelay while the energisation of the detector itself builds up. However,in severe overload conditions, known overload detectors may not respondadequately to a severe short-circuit condition at the power supplyoutput. For example, if the overload detector is responsive to Vout, asevere short-circuit at the load will pull Vout down and keep itrelatively low during a prolonged turn-on time in spite of rapidlyincreasing power supply output current. The overload sensor will not beenergised to detect an abnormal condition during the turn-on phase fastenough to prevent the power dissipation damaging the power supply outputswitch and/or also the load supplied with power (wire harness and/orPCB).

A need exists for power supply apparatus with rapid overload detectionduring the turn-on phase, especially against severe overload conditions.

SUMMARY OF THE INVENTION

The present invention provides a power supply switching apparatus asdescribed in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of over-current protection in apower supply switching apparatus in accordance with one embodiment ofthe invention, given by way of example,

FIG. 2 is graph of current detection thresholds as a function of appliedvoltage in operation of the over-current protection of FIG. 1.

FIG. 3 is a schematic diagram of a round-shaping circuit in a knownpower supply switching apparatus.

FIG. 4 is a graph of voltage as a function of time in the case of anormal load applied to the output of the power supply switchingapparatus of FIG. 1 and FIG. 3.

FIG. 5 is a graph of voltage as a function of time in the case of asevere overload applied to the output of the known power supplyswitching apparatus of FIG. 3.

FIG. 6 is a schematic diagram of a round-shaping circuit and severeoverload detector in a power supply switching apparatus as shown in FIG.1 in accordance with an embodiment of the present invention.

FIG. 7 is a graph of voltage as a function of time in the case of asevere overload applied to the output of the power supply switchingapparatus of FIG. 6.

FIG. 8 is a schematic diagram of a severe overload detector in a powersupply switching apparatus as shown in FIG. 1 in accordance with anotherembodiment of the present invention.

FIG. 9 is a graph of voltage as a function of time in the case of asevere overload applied to the output of the power supply switchingapparatus of FIG. 8.

FIG. 10 is graph of currents and thresholds as a function of appliedvoltage in operation of the severe overload and over-current protectionof FIG. 8.

FIG. 11 is a block schematic diagram of fault management circuit in apower supply switching apparatus in accordance with an embodiment of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows the overall architecture of power switching control andover-current protection in a power supply switching apparatus both inaccordance with one embodiment of the invention and in a known powersupply switching apparatus. The switching apparatus shown is suitablefor switching incandescent light bulbs in an automotive application withnominal battery supply voltage of 12 volts although the apparatus canalso have other applications and is applicable at other batteryvoltages.

The apparatus includes two semiconductor dies, a power die 2 and acontrol die 4. The dies are supplied with power between a positive powerrail 6 and ground 8. It is possible alternatively to integrate the powersupply and control functions on a single die.

The power die 2 comprises an array of field effect transistor (‘FET’)power cells 10 of metal-oxide-Silicon (‘MOS’) technology connected forswitching and conducting the current lout to be switched and aphysically similar sense FET cell 12 connected for conducting a sensecurrent Isense. The FETs 10 and 12 have gates connected together toreceive a gate signal on a line 14 from the control die. The FETs 10 and12 have drains connected to the power rail 6 and sources connected tosupply current to the control die 4 over lines 15 and 16. The signalapplied to the gates serves to switch the FETs 10 and 12 on and off andalso to control their resistance during the switching on phase.Switching on the array of FETs 10 applies the battery voltage of thepower line 6 to an output terminal 17 connected to the line 15 and towhich the load may be connected. The array of FETs 10 contains asufficient number of FET cells, in one embodiment 10,000 cells, to carrythe current required to supply the load, whereas a single cell issufficient in this embodiment to carry the much smaller sense current inthe line 16.

The control die 4 includes an amplifier 18 having differential inputsconnected to the lines 15 and 16, the power supply for the amplifierbeing provided by a connection 20 to the line 16 of the sense FET 12, sothat power is supplied to the amplifier only when the sense FET isconducting. The amplifier 18 is only operational for a voltage greaterthan 3 volts. The line 16 is also connected over a line 22 to the drainof a FET 24 whose source is connected through a constant current element26 to ground 8. The connection between the FET 24 and the constantcurrent element 26 is connected to a Schmidt trigger 28 that provides afault signal OCLO indicative of a ‘soft overload’ condition in the eventof a resistive overload condition of the load between the outputterminal 17 and ground as shown at 36. The source of the FET 24 is alsoconnected through a diode 30 and through a constant current element 32to ground 8. The connection between the diode 30 and the constantcurrent element 32 is also connected to a Schmidt trigger 34 thatprovides a fault signal OCHI indicative of a ‘hard overload’ conditionin the event of a more severe overload condition of the load, since thethreshold voltage of the diode prevents actuation of the Schmidt trigger34 until the output of the amplifier 18 has reached a higher voltage. Itwill be appreciated that so-called constant current elements like 26 and32 present a small impedance when the current supply applied isinsufficient to reach the nominal constant current of the element andtheir impedance increases once the nominal current is reached, so as tomaintain the current at the nominal level. In another embodiment of thepresent invention, the constant current elements 26 and 32 are replacedby resistors, which present constant impedance.

In one example of an application of the invention, the parametersdefining the ‘soft overload’ condition are set to correspond to anabnormally low resistance of the load, which may be caused by the usageof a bulb of wrong current capacity in the lamp, for example, and theparameters defining the ‘hard overload’ condition are set to correspondto a short circuit at the lamp socket so that the load presented to theswitch is virtually as low as the very low resistance of the cableconnecting the socket to the switch, for example.

As illustrated in FIG. 2, the over-current protection shown in FIG. 1 iseffective in operation to detect load current through the outputterminal 17 exceeding a threshold value 38 when the voltage supplied bythe lines 16 and 20 to the amplifier 18 exceeds 3 volts up to themaximum voltage Vpwr. As shown by the hatched area 40, the over-currentprotection is not effective when the voltage supply to the amplifier 18is below 3 volts.

In a known power supply switching apparatus having over-currentprotection of the kind shown in FIG. 1, the gate signal applied to theline 14 is generated by a circuit of the kind illustrated in FIG. 3. Abinary switching command signal, generated in response to a manual orsemi-automatic input by a command signal generator (not shown), andwhich may be a pulse-wave modulated signal if desired, is applied to aninput 42 of a gate driver circuit 44 to generate the signal applied tothe line 14. The voltage Vout at the output terminal 17 is applied overa line 45 to a round-shaping circuit 46, which adjusts the current Igatesupplied by the gate driver 44, so as to obtain a smooth outputslew-rate, that is to say a progressive turn-on of the power supply fromthe rail 6 through the output switch array 10, in dependence on theoutput voltage (Vout).

In normal operation with no overload, the known power supply switchingapparatus with the gate signal generator of FIG. 3 functions as shown inFIG. 4, which illustrates the variation of voltages in the apparatus asa function of time. Initially, as long as the switching command signalon line 42 is de-asserted, the voltage Vgate on the line 14 applied tothe gates of the FETs 10 and 12 is low, as shown in chain-dotted lines,the FETs are switched off and Vout, shown in full lines, is zero, as isVsense, shown in dotted lines. When the switching command signal on line42 is asserted, Vgate starts to increase so as to reduce progressivelythe on-resistance of the FETs 10 and 12, increasing Vout (and Vsense)progressively in the presence of a normal load. However, as long as Voutis below a threshold value 48, the slew rate, that is to say the rate ofincrease in Vout, is kept low to reduce the switching electromagneticemissions by limiting the gate current Igate in the line 14. In oneexample, Igate is divided by a factor of 4 for Vout<0.5V relative to itsvalue for Vout>0.5V.

Such a characteristic is satisfactory in the cases of a normal load and‘soft overload’ or ‘hard overload’ conditions. However, a ‘severeoverload’ condition such as may be caused by a short circuit at theoutput terminals of the switch itself can present an even lowerimpedance to the switch, without even the resistance of the cableconnecting the switch to the lamp to limit the current drawn. In thecase of a severe short-circuit to ground 36, as illustrated in FIG. 5,the voltage Vout at the output terminal 17 is pulled down close toground (Vout=0), with the result that the current Igate in the line 14supplying the gate of the powerMOS FET 10 stays at a reduced value underthe control of the round-shaping circuit 46. Also the Gate-Sourcecapacitance of the PowerMOS FET 10 has to be charged, since the sourcevoltage of the FET 10 is held down close to ground, adding capacitanceon the gate node 14. This leads to a gate voltage slew rate divided byfactor of about 10, instead of a factor of about 4 in normal operationof the example quoted above, so that the circuit takes about 300 μsec toreach the situation where Vsense=3V and Vgate=5.5V. Energising theover-current detection of the apparatus shown in FIG. 1 from the currentIsense that the senseFET 12 starts to supply needs sufficient voltage onthe SenseFet 12 (˜3.5V) & Gate (˜5.5V) and hence on the amplifier 18 tobe functional. So over-current detection is not functional during a TurnON time of about 600 μsec as shown in FIG. 5. This reaction is not fastenough to prevent the power dissipation damaging the power supply outputswitch and/or also the load supplied with power which can reach 3 kW forexample during the 600 μsec delay, which is capable of causingsignificant damage.

In the embodiment of the present invention illustrated by FIG. 6, in theevent of an overload to ground at the output terminal 17, theround-shaping circuit is responsive to the voltage Vsense on the line16, applied to an input of the round-shaping circuit over a line 50, aswell as to the output voltage Vout. The round-shaping circuit 46includes an OR circuit 52 responsive to the relative values of thevoltage Vsense on the line 16 applied over the line 50 and the outputvoltage Vout applied over a line 54.

In operation, and referring also to FIG. 7, the OR circuit 52 provides asignal Igate_adjust to the gate driver 44 to accelerate the currentIgate in the line 14 as soon as the voltage Vsense reaches the thresholdvoltage 48, at which the OR circuit 52 is operational, as shown at 58 inFIG. 7. The Schmidt trigger 34 then asserts the Hard overload signalOCHI once Vsense reaches the threshold of the zone 40 at which theamplifier 18 becomes operational, as shown at 60 in FIG. 7, even if theoutput voltage Vout is still lower than the threshold 48. Thisacceleration of the increase in the voltage Vsense in the line 16shortens the time taken for the amplifier 18, FET 24 and Schmidt trigger34 to become functional and generate a fault signal reporting the faultcondition.

In the embodiment of the present invention illustrated by FIGS. 8 and 9,the round-shaping circuit is again responsive to the voltage Vsense onthe line 16, applied to an input of the round-shaping circuit over aline 50, as well as to the output voltage Vout. In this embodiment, theconstant current source 32 is replaced by a reference resistor 62. Thesense voltage Vsense and the output voltage Vout are compared in acomparator 63 to give a comparison between the overload resistanceR_short and the resistance Rref of the reference resistor 62 divided by‘n’ where n is the ratio of the number of cells in the PowerMOS FET 10to the number of cells in the sense FET 12. A threshold circuit 64generates a threshold signal that is asserted if the value of Vsenselies between a lower threshold of detection 69 (1 volt in this example)at which the comparator 63 becomes operational and the threshold of thezone 40 where over-current detection becomes functional (3 volts in thisexample). The outputs of the threshold circuit 64 and of the comparator63 are applied to an AND circuit 66 having a dedicated output 68providing a severe short circuit fault signal which is asserted in therange where the value of Vsense is between the thresholds 69 and 40 ifthe output of comparator 63 is asserted.

As shown in the graph of voltage against time in FIG. 9, in theembodiment of the present invention shown in FIG. 8, a severe shortcircuit condition can be detected and signaled at a moment 71 whenVsense reaches the threshold 69, soon after the moment 58 when the sensevoltage Vsense reaches the lower threshold 48 and the current Igate isincreased, without needing to wait until the moment 60 when the sensevoltage Vsense reaches the upper threshold of the zone 40 and theamplifier 18, FET 24 and Schmidt trigger 34 become operational. Severeshort circuits can be detected in an example of this embodiment of theinvention during the period 40 while over-current detection is still notfunctional within a time of about 100 μsec from application of the gatesignal on the line 14. This reaction time is fast enough to prevent thepower dissipation damaging the power supply output switch or the loadsupplied with power and can limit the peak output power to 500 W forexample even in presence of a severe short circuit.

The operation of the apparatus of FIG. 8 is shown for various operatingconditions in the graph of current against voltage of FIG. 10. The line70 in FIG. 10 represents the output current lout in case of a severeshort circuit at the output terminal 17. As shown in dotted lines, inthe absence of protection in the zone 40, the output current wouldrapidly run away and cause damage but the condition can be detected atmoment 71 by the comparator 63 and the AND circuit 66 A less severeoverload will be detected if the comparator 63 and the AND circuit 66signal a fault condition later while the value of Vsense is between thethresholds 48 and 40, between moments 71 and 60.

After the moment 60, when the amplifier 18 and Scmidt triggers 28 and 34become operational, a resistive overload at the output terminal 17 willbe detected by the over-current protection shown in FIG. 1, as shown bythe line 72 in FIG. 10. Although the time taken to signal the faultcondition is longer than for the case of severe short circuit detection,the output current involved is lower and less prone to cause damage. Theline 74 illustrates the case of a normal load at the output terminal 17.

The fault signals may used in various ways by protection functions tolimit the output current lout in fault conditions and prevent damage.FIG. 11 shows schematically a protection apparatus in one example of anembodiment of the invention. In the protection apparatus of FIG. 1, thesignals OCLO and OCHI from the Schmidt triggers 28 and 34 and the severeoverload signal from the output 68 of the AND circuit 66 are applied torespective inputs of a fault management circuit 78. The outputs of thefault management circuit 78 control the gate driver 44 in case ofassertion of a fault signal. The occurrence of a soft overload signalOCLO asserts a signal on a line 80 to trigger a normal turn off of thepower switch 10, while the occurrence of a hard overload signal OCHI ora severe overload signal asserts a signal on a line 82 to trigger arapid turn off of the power switch 10. A further distinction may be madeif desired, as in patent application PCT/EP2004/014895, between a hardoverload, where repeated attempts to turn the switch on again may bemade and a severe overload where the power switch 10 is turned offdefinitively and no attempt is made to turn the switch on again.

1. Power supply switching apparatus comprising: an output switch forsupplying power from a power supply to a load connected to an outputterminal; a driver for controlling turn-on of said output switch; and acontrol signal generator for controlling said driver to produce adesired progressive turn-on characteristic, said control signalgenerator including an overload detection circuit responsive to aparameter of the load relative to a reference signal to provide a firstfault signal in case of detection of an overload condition after aturn-on phase of said output switch, wherein said control signalgenerator is responsive to said reference signal to activate saidoverload detection circuit to respond to an overload condition at saidload and provide a second fault signal at least during said turn-onphase of said output switch even in presence of a severe overloadcondition at the output terminal, wherein said overload detectioncircuit comprises a first detector activated at a first voltage fordetecting resistive overload and a second detector activated at a secondvoltage different from said first voltage for detecting the severeoverload.
 2. Power supply switching apparatus as claimed in claim 1,wherein said overload detection circuit is responsive to a parameterrelating to a current in said load at least after said turn-on phase. 3.Power supply switching apparatus as claimed in claim 1, wherein saiddriver is arranged to turn on supply of power to said overload detectioncircuit when starting said turn on phase.
 4. Power supply switchingapparatus as claimed in claim 3, wherein said reference signal isarranged to be supplied to power said overload detection circuit, andsaid driver is arranged to turn on said reference signal when startingsaid turn on phase.
 5. Power supply switching apparatus as claimed inclaim 1, and including fault management circuit responsive to saidoverload detection circuit for turning said output switch off, saidfault management circuit being arranged to respond more rapidly to afault signal in case of detection of an overload condition during saidturn-on phase than to a fault signal in case of detection of an overloadcondition after said turn-on phase.
 6. Power supply switching apparatuscomprising: an output switch for supplying power from a power supply toa load connected to an output terminal; a driver for controlling turn-onof said output switch; a control signal generator for controlling saiddriver to produce a desired progressive turn-on characteristic, saidcontrol signal generator including an overload detection circuitresponsive to a parameter of the load relative to a reference signal toprovide a first fault signal in case of detection of an overloadcondition after a turn-on phase of said output switch, wherein saidcontrol signal generator is responsive to said reference signal toactivate said overload detection circuit to respond to an overloadcondition at said load and provide a second fault signal at least duringsaid turn-on phase of said output switch even in presence of a severeoverload condition at the output terminal; and a fault managementcircuit responsive to said overload detection circuit for turning saidoutput switch off, said fault management circuit being arranged torespond more rapidly to a fault signal in case of detection of anoverload condition during said turn-on phase than to a fault signal incase of detection of an overload condition after said turn-on phase. 7.Power supply switching apparatus as claimed in claim 6, wherein saidcontrol signal generator is responsive to a parameter of power supply tosaid load as well as to said reference signal at least during saidturn-on phase so as to activate said overload detection circuit torespond to an overload condition.
 8. Power supply switching apparatus asclaimed in claim 7, wherein said parameter of power supply to said loadto which said control signal generator and said overload detectioncircuit are responsive during said turn-on phase comprises a voltageapplied to said output terminal.
 9. Power supply switching apparatus asclaimed in claim 8, wherein said overload detection circuit comprises adetector responsive to a parameter related to a severe overload on saidoutput terminal during said turn-on phase and related to an impedance atsaid load relative to a reference impedance.
 10. Power supply switchingapparatus as claimed in claim 6, wherein said overload detection circuitis responsive to a parameter relating to a current in said load at leastafter said turn-on phase.
 11. Power supply switching apparatus asclaimed in claim 6, wherein said overload detection circuit comprises areference signal generator for generating said reference signal, saidoutput switch and said reference signal generator comprisingrespectively an output switch transistor and a reference signalgenerator transistor having control electrodes, and said driver isarranged to supply a controlled turn-on signal to said controlelectrodes of both said output switch transistor and said referencesignal generator transistor.
 12. Power supply switching apparatus asclaimed in claim 6, wherein said driver is arranged to turn on supply ofpower to said overload detection circuit when starting said turn onphase.
 13. Power supply switching apparatus as claimed in claim 12,wherein said reference signal is arranged to be supplied to power saidoverload detection circuit, and said driver is arranged to turn on saidreference signal when starting said turn on phase.
 14. A method forproviding overload detection in a power supply switching apparatus, themethod comprising: supplying, at an output switch, power from a powersupply to a load connected to an output terminal; controlling, at adriver, turn-on of said output switch; and controlling the driver toproduce a desired progressive turn-on characteristic of the outputswitch; during a turn-on phase of the output switch: activating anoverload detection circuit in response to a reference signal;responding, at the overload detection circuit, to a first overloadcondition at the load; and providing a first fault signal in response toa severe overload condition at the output terminal; and after theturn-on phase of the output switch: monitoring a parameter of the loadrelative to the reference signal; and providing a second fault signal inresponse to a detection of a second overload condition based on theparameter of the load relative to the reference signal.
 15. The methodclaim 14, further comprising: responding to a parameter related to thesevere overload on the output terminal during the turn-on phase andrelated to an impedance at the load relative to a reference impedance.16. The method of claim 15, wherein the parameter of power supply to theload to which the control signal generator and the overload detectioncircuit are responsive during the turn-on phase comprises a voltageapplied to said output terminal.
 17. The method of claim 16, furthercomprising: responding to a parameter related to a severe overload onsaid output terminal during said turn-on phase and related to animpedance at said load relative to a reference impedance.
 18. The methodof claim 14, further comprising: responding to a parameter relating to acurrent in said load at least after said turn-on phase.
 19. Power supplyswitching apparatus comprising: an output switch for supplying powerfrom a power supply to a load connected to an output terminal; a driverfor controlling turn-on of said output switch; and a control signalgenerator for controlling said driver to produce a desired progressiveturn-on characteristic, said control signal generator including anoverload detection circuit responsive to a parameter of the loadrelative to a reference signal to provide a first fault signal in caseof detection of an overload condition after a turn-on phase of saidoutput switch, wherein said control signal generator is responsive tosaid reference signal to activate said overload detection circuit torespond to an overload condition at said load and provide a second faultsignal at least during said turn-on phase of said output switch even inpresence of a severe overload condition at the output terminal, whereinsaid control signal generator is responsive to a parameter of powersupply to said load as well as to said reference signal at least duringsaid turn-on phase so as to activate said overload detection circuit torespond to an overload condition, wherein said parameter of power supplyto said load to which said control signal generator and said overloaddetection circuit are responsive during said turn-on phase comprises avoltage applied to said output terminal, and wherein said overloaddetection circuit comprises a detector responsive to a parameter relatedto a severe overload on said output terminal during said turn-on phaseand related to an impedance at said load relative to a referenceimpedance.
 20. Power supply switching apparatus comprising: an outputswitch for supplying power from a power supply to a load connected to anoutput terminal; a driver for controlling turn-on of said output switch;and a control signal generator for controlling said driver to produce adesired progressive turn-on characteristic, said control signalgenerator including an overload detection circuit responsive to aparameter of the load relative to a reference signal to provide a firstfault signal in case of detection of an overload condition after aturn-on phase of said output switch, wherein said control signalgenerator is responsive to said reference signal to activate saidoverload detection circuit to respond to an overload condition at saidload and provide a second fault signal at least during said turn-onphase of said output switch even in presence of a severe overloadcondition at the output terminal, wherein said overload detectioncircuit comprises a reference signal generator for generating saidreference signal, said output switch and said reference signal generatorcomprising respectively an output switch transistor and a referencesignal generator transistor having control electrodes, and said driveris arranged to supply a controlled turn-on signal to said controlelectrodes of both said output switch transistor and said referencesignal generator transistor.